1. Field of the Invention
Example embodiments of the present invention relate to equalizers and methods for channel equalization.
2. Description of the Conventional Art
Equalizers may be used to compensate for distortion of signals input to, or output from, various types of signal transmission and/or receipt systems. Equalizers may include a filtering circuit, which may improve performance of a communications system, for example, by suppressing channel noise and/or distortion. Channel noise and/or distortion may be caused by delay of signals input to, or output from, a communications system, for example, via multiple paths. The filtering circuit may use filtering coefficients in order to suppress channel noise and/or channel distortion. The values of the filtering coefficients may be determined based on channel estimation information and/or noise signals distributed over upper and/or lower frequencies of main data signals, (e.g., delayed signals). Filtering coefficients corresponding to noise signals may be set to values such that respective noise signals may be suppressed.
FIG. 1 is a block diagram illustrating an example a conventional equalizer 10. Referring to FIG. 1, the conventional equalizer 10 may include a filtering circuit 11 and a coefficient updating circuit 12. The filtering circuit 11 may include a plurality of filter cells TS1 through TSM (where M is an integer) and an adder 16. Each of the filter cells TS1 through TSM may include a data buffer 13, a coefficient buffer 14, and a multiplier 15. The data buffer 13 for each of the filter cells TS1 through TSM and the coefficient updating circuit 12 may receive an input data signal Din. The coefficient updating circuit 12 may estimate channels, which may vary with respect to the input data signal Din, and may generate filtering coefficients Co1 through CoM (where M is an integer) based on the estimated channels.
For example, if the filtering circuit 11 includes 9 filter cells, the input data signal Din, and the filtering coefficients Co1 through Co9, the multiplication signals X1 through X9 obtained using the 9 filter cells may be illustrated in FIG. 2. Referring to FIG. 2, the input data signal Din may include main data signals MS1 and MS2 and noise signals Eo1 through Eo4. The noise signals Eo1 through Eo4 may be, for example, delayed main data signals MS1 and MS2, which may be generated when transmitting the main data signals MS1 and MS2, for example, via multiple paths. In order to suppress the noise signals Eo1 through Eo4, the coefficient updating circuit 12 may generate the filtering coefficients Co1, Co2, Co4, and Co7, which may offset the noise signals Eo1 through Eo4, respectively. The multipliers 15s may suppress the noise signals Eo1 through Eo4 by multiplying the noise signals Eo1 through Eo4 by the filtering coefficients Co1, Co2, Co4, and Co7, respectively. The multiplication signals X1, X2, X4, and X7, may have values of, for example, zero, as shown in FIG. 2.
In order to output the main data signals MS1 and MS2 properly (e.g., unchanged), as the multiplication signals X5 and X9, respectively, the coefficient updating circuit 12 may generate filtering coefficients Co5 and Co9 such that the multiplication signals X5 and X9 obtained by multiplying the main data signals MS1 and MS2 by the filtering coefficients Co5 and Co9, respectively, may have the same, or substantially the same, values as the main data signals MS1 and MS2.
Less precise channel estimation may cause filtering coefficients Co3, Co6, and Co6 whose values may be substantially zero, but may not be equal to zero, to be generated by the coefficient updating circuit 12. The multiplication signals X3, X6, and X8, obtained by multiplying the main data signals or noise signals by the filtering coefficients Co3, Co6, and Co6, respectively, may be input to the adder 16 such that a distorted version of the input data signal Din may be output as an output data signal Dout.